1. FIELD OF INVENTION
The present invention relates to a system controller, a control system and a system control method.
2. RELATED BACKGROUND ARTS
It has been a known technology to raise a reliability of a system in which a plurality of CPUs are arranged such that when one of the CPU is down, the other CPU is started without interrupting operations of the system. Such technology is disclosed, for example, in Japanese laid open patent No. 5-134932.
Hereinafter an outline of the disclosed technology is described as referring to FIG. 5.
FIG. 5 is a block diagram illustrating the outline of the disclosed technology.
A reference numeral “1” is a first CPU board, “2” is a second CPU board, “10” is a common bus, “11” is a CPU, “12” is an arbiter to arbitrate between an access requirement from the CPU 11 and an access requirement from a CPU 21, “13” and “14” are bus gates for determining flowing directions of data under the control of the arbiter 12, “15” is an error detection circuit for monitoring errors in one of the CPUs presently accessing to a memory, “16” is a memory for storing processed data, “17” is an internal bus, “18” is a ready state monitoring circuit, “21” is the CPU, “22” is an arbiter, “23” and “24” are bus gates, “25” is an error detection circuit, “26” is a memory, “27” is an internal bus and “28” is a ready state monitoring circuit.
The first CPU board 1 comprises the CPU 11, the arbiter 12, the bus gates 13 and 14, the error detection circuit 15 and the memory 16, and the second CPU board 2 comprises the same components as those of the first CPU board 1.
The first CPU board 1 and the second CPU board 2 are arranged via the common bus 10 such that if an error is detected when the memory 16 of the first CPU board 1 is accessed, the arbiter 12 controls the bus gates 13 and 14 so as to assign the access right to the second CPU board 2.
In addition to the above-described technology, other technology to utilize a reflect memory as a common memory, which can be accessed from a plurality of CPUs, and the like have been known.
However, in the above-mentioned technologies, since the access right is switched in accordance with the detected error in one CPU by the error detection circuit, there is a brief time lag from a time when the error is caused to a time when the error is detected and the access right is switched to the other CPU board. Sometimes problems are caused due to such time lag.
For example, if a CPU is down while processing data and writing processed data in a memory, the processed data by the CPU are lost and only data written in the memory remain. Since an accident that the CPU is down is detected after the brief time lag, it is difficult to judge to what extent the processed data are stored in the memory. Therefore, after the memory is returned a prior state before processing, the other CPU must be started working for processing and writing data from scratch. Alternatively, the other CPU must be started so as to succeed to processed data by the down CPU, after judging to what extent the data remain in the memory as checking the data written in the memory.
Due to such time lag, it takes time to process data and a highly complicated function to switch the CPU from down one to the other is required. Further, in order to avoid such drawbacks a complicated system or software with high performance is required, so that a considerable amount of costs are required or a stability of the system must be sacrificed.
When a plurality of CPUs are employed, the reflect memory, which is expensive, must be employed as the common memory for the CPUs so that further costs are required.
The present invention is carried out in view of the above-mentioned problems in order to provide an inexpensive, highly stable system controller, a control system and a system control method capable of storing all information and past record when one of the CPUs is down and capable of switching the access right without any time lag.